Beyond the Controller: IvyLinkβ’ CXL Memory Fabric Architecture
Why standard CXL controllers aren't enough for memory pooling β and how our Application Layer Fabric delivers pooling, sharing, and tiering with deterministic latency.
Beyond the Controller: IvyLinkβ’ CXL Memory Fabric Architecture
Standard CXL controllers give you a compliant link. But memory pooling demands more β dynamic allocation, QoS guarantees, multi-host cache coherence, and RAS that doesnβt exist in the spec.
The Controller Gap
CXL 3.0 spec defines the wire protocol. But a standard controller gives you:
- Link initialization and training
- Transaction layer (PCIe + CXL.mem/cache)
- Basic register interface
What it doesnβt give you:
- Memory Pool Manager β dynamic allocation, tiering, QoS across hosts
- Fabric Manager β topology discovery, routing, congestion control
- Coherency Agent β multi-host cache coherence for CXL.cache
- Security/RAS Agent β SPDM, telemetry, predictive failure
Hyperscalers build these in-house. We productized them.
IvyLinkβ’ CXL Memory Fabric Architecture
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β CXL Memory Fabric β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β βββββββββββββββ βββββββββββββββ βββββββββββββββ β
β β CXL 3.0 β β CXL 3.0 β β CXL 3.0 β β
β β Controller β β Controller β β Controller β β
β ββββββββ¬βββββββ ββββββββ¬βββββββ ββββββββ¬βββββββ β
β β β β β
β ββββββββββββββββββΌβββββββββββββββββ β
β βΌ β
β βββββββββββββββββββββββββββ β
β β Memory Pool Manager β β Our IP β
β β (Allocation/Tiering/QoS)β β
β βββββββββββββ¬ββββββββββββββ β
β βΌ β
β βββββββββββββββββββββββββββ β
β β Fabric Manager β β Our IP β
β β (Topology/Routing/QoS) β β
β βββββββββββββ¬ββββββββββββββ β
β βΌ β
β βββββββββββββββββββββββββββ β
β β Coherency Agent β β Our IP β
β β (Multi-host CXL.cache) β β
β βββββββββββββ¬ββββββββββββββ β
β βΌ β
β βββββββββββββββββββββββββββ β
β β Security/RAS Agent β β Our IP β
β β (SPDM/Telemetry) β β
β βββββββββββββββββββββββββββ β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
Key Differentiators
1. Memory Pool Manager
Dynamic allocation with QoS guarantees β not best-effort:
- Guaranteed bandwidth per tenant via weighted fair queuing
- Latency isolation β tail latency < 500ns even under contention
- Tiering policies β hot/cold data migration between HBM/DDR/CXL.mem
2. Fabric Manager
CXL 3.0 enables multi-level switching. Our fabric manager handles:
- Topology discovery (CXL 3.0 hierarchy)
- Adaptive routing with congestion avoidance
- QoS-aware routing β latency-sensitive traffic gets priority paths
3. Coherency Agent
CXL.cache enables multi-host coherence. Our agent implements:
- Directory-based coherence with distributed directories
- Snoop filter reducing broadcast traffic by 89%
- Conflict resolution for concurrent writes from multiple hosts
4. Security/RAS Agent
Production hardening beyond the spec:
- SPDM 1.2 for device authentication and measurement
- Telemetry streaming β latency histograms, error counters, predictive failure
- Predictive failure β ML-based wear-out detection for CXL memory modules
Silicon Validation (130nm CMOS5L)
| Component | Area | Power @ 32 GT/s |
|---|---|---|
| CXL Controller | 2.1 mmΒ² | 850 mW |
| Memory Pool Manager | 0.4 mmΒ² | 45 mW |
| Fabric Manager | 0.3 mmΒ² | 32 mW |
| Coherency Agent | 0.5 mmΒ² | 58 mW |
| Security/RAS | 0.2 mmΒ² | 18 mW |
| Total | 3.5 mmΒ² | ~1.0 W |
Business Model: Solution + Service
We donβt just sell RTL. We deliver:
- Customized RTL β tailored to your topology (2/4/8-socket, switch topology)
- Firmware stack β Linux kernel driver, SPDM stack, telemetry agent
- Integration service β 3-month bring-up support
- SLA-backed support β 24/7 for hyperscalers
Learn more about IvyLinkβ’ CXL Memory Fabric β Product Page | Contact Sales